1. Field of the Invention
The present invention relates to an optimization technique for dynamic compile processing in which a program is compiled during execution of the program. More specifically the present invention relates to a compiling method, a program and an information processing apparatus for a dynamic compiler to optimize compiled code.
2. Description of the Related Art
Conventionally, virtual machines (VMs) emulate computer operations and some are configured such that an interpreter interprets machine code at a low speed; then a dynamic compiler generates intermediate code from a trace, which is an instruction sequence described in the machine language, optimizes the intermediate code, and generates compiled code from the optimized intermediate code; and then the interpreter executes the compiled code.
Generally, the compilation target machine code contains various branch instructions, such as a relative branch instruction and an indirect branch instruction. A relative branch instruction designates a branch target by using an offset from the address of the relative branch instruction. An indirect branch instruction designates a branch target by using a value of a register incorporated in a processor such as a CPU and an offset from the value of the register.
The value of the register used in an indirect branch instruction varies at every run of the program. In addition, the virtual machine maps a physical address to a virtual address that also varies at every run of program. For these reasons, when the compilation target machine code contains an indirect branch instruction the compiled code needs to be run while checking whether an address predicted as a branch target of the indirect branch instruction matches with a memory address of a branch target that the processing is actually branched to (referred to as an actual branch target).
In this respect, Japanese Patent Application Publication No. 2002-259135 discloses a compilation optimization method using guard code for checking whether a memory address of an actual branch target matches a memory address predicted as a branch target of an indirect branch instruction. In such a conventional optimization method guard code, as shown in FIG. 8, is embedded in compiled code and thereby the compiled code is run while checking whether the memory address of the actual branch target matches the memory address predicted as the branch target of an indirect branch instruction.
Herein below FIG. 8 is referred to. Guard code, as shown in FIG. 8, is used to determine whether the virtual page address (branch-target-virtual-address&˜0xfff) of the actual branch target and the current virtual page address (current-virtual-pc&˜0xfff) are the same to thereby determine whether the indirect branch instruction causes page boundary crossing. If the indirect branch instruction does not cause page boundary crossing, it is determined whether a page offset address (branch-target-virtual-address & 0xfff) of the virtual address of the actual branch target matches with a page offset address (next-physical-pc-on-trace & 0xfff) of the branch address predicted as the branch target of the indirect branch instruction. If these addresses match with each other, that is, if the branch prediction succeeds, the execution of the compiled code is continued. On the other hand, if the addresses do not match with each other, the execution of the compiled code is terminated (side-exit trace). But if the indirect branch instruction does cause page boundary crossing the virtual address of the actual branch target is converted into a physical address corresponding to the virtual address. Then it is determined whether the physical address matches with a physical address predicted as the branch target of the indirect branch instruction. If these addresses match with each other, the execution of the compiled code is continued. If the addresses do not match with each other, the execution of the compiled code is terminated (side-exit trace).
However, the optimization method described in Japanese Patent Application Publication No. 2002-259135 requires guard code to be embedded in compiled code for each indirect branch instruction. As shown, the guard code is used to check whether an address predicated as a branch target of the indirect branch instruction matches with a memory address of the actual branch target. For this reason, in every run of compiled code, the guard code can cause a delay in the execution processing of the program due to an increase in CPU load, and also can lead to wasteful consumption of memory.
The present invention has been made to solve the foregoing problems, and has an objective to provide a compiling method, a program and an information processing apparatus that are capable of lowering CPU load and decreasing memory consumption by reducing pieces of guard code each of which is to be embedded in compiled code for an indirect branch instruction included in machine code to be compiled.